Showing posts with label Master Thesis. Show all posts
Showing posts with label Master Thesis. Show all posts

Tuesday, 18 August 2009

Phd/Master Thesis in France

Four Phd/Master thesis positions in France
TITLES:

- Physical modeling and improved performance of silicides on the electrical behavior of semiconductor components.
- Application of optical diffraction structures on a repetitive measurement of critical dimensions
- Development of new architecture NVM memory cells
- Introduction of technology nanocrystals in non-volatile memory integrated circuits


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Education Level Required - BAC +5 (INGENIEUR, DESS, DEA ...).

How to Apply
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Phd/Master Thesis in France

ABOUT THESIS: PHYSICAL CHARACTERIZATION 2D-3D DEFECTS IN ADVANCED CMOS TECHNOLOGY

The control of the manufacturing yields of CMOS devices requires the use of analytical high performance such as transmission electron microscopy. In this area, a first CIFRE thesis (A. Demolliens, 2006-2009) has produced many developments for analysis of nano dimensions dobjets: new procedures for sample preparation (low-voltage FIB, cleaning "ion", capping resin, etc. ...) and observe new modes (HAADF, HRSTEM etc ...). To cover physical analysis relevant to even lower levels, it is essential to these developments by use of microscopy UHR (ultra-microscope with high resolution correction daberrations). This technique allows to reach a spatial resolution of less than Långström and saffranchir effects of relocation during measurement of very thin oxides (thickness less than 30 Å). For this technique, sample preparation is even more critical methodologies and observations are to be developed.

Although electron microscopy UHR addresses the problem of spatial resolution, it does not allow observation dimensional (3D) to a sub-nanometer scale. Indeed, for the TEM observation UHR, lépaisseur of léchantillon must be as low as possible (although less than 50 nm) and observation tends to be two-dimensional. Although this type of observation is well suited to measure oxide or very fine grid to the observation of defects in silicon, it is less suited to linvestigation defects or 3D nanoscale characterization of thin film deposited on a rough surface ( ONO typically on poly-Si).
New techniques should be explored in order to access such information. In this context, it is envisaged to develop analysis:
Tomography "X-Ray nano" using a conventional X-ray (spatial resolution <50>
TEM tomography or HRSTEM (sub-nanometer resolution);
Tomography coupled with a probe atomic (atomic resolution).
It will be necessary to devalue the potential and limitations of each of these techniques and to develop adequate sample preparations associated.

In addition to the analysis of laboratory equipment, it is also provided access to a ring producing synchrotron X-ray beams of high quality in terms of selectivity in energy, brilliance and parallelism. The microtomographie originally intended for the medical field, is increasingly used to study the volume of materials. Using an X-ray beam produced in a synchrotron ring improves image quality in terms of spatial resolution, signal to noise ratio and quantitative exploitation. The total acquisition time can range from a few seconds to an hour. The microtomographie can be combined with imaging phase is in a qualitative way to improve contrast, more quantitatively in the way holotomographie.
Thus, it is not considered routine experiments on this type of instrument, but to isolate the impact of the beam quality of the reconstructed 3D image and the detection of defects in volume.

In summary, the proposed thesis work seeks to understand the techniques of physical characterization of the most advanced efforts to detect, locate and identify structural defects in volume likely dimpacter operation and / or the reliability of memory devices incorporating CMOS technology of last generation .

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Education Level Required - BAC+5 (INGENIEUR,DESS,DEA...) Desired Competencies are - Physico-Chemistry, Physics Of Semiconductors, Adaptability, Flexibility.

How to apply:
Apply here

Apprentice for Technical Development/Support in France

Job description:

Within the Design Tools and Methodologies team, in charge of defining, develop and support Design Flows specific to the development of Imaging circuits based on commercial and internally developed CAD tools, the goal of the internship is to develop CAD tools to improve the methodology which is being used IPs designs and for System On Chip Physical Implementation and verification.

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Education Level Required - BAC+3 (LICENCE,...) Desired Competencies are - Digital Electronics.The Other skills required are Unix shell, C/C++, perl, tcl programming, basic knowledge of verilog and vhdl

How to apply ?

Apply here
 
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